PROVIDING WORLD-CLASS ASSEMBLY AND TEST SERVICES FOR THE SEMICONDUCTOR AND ELECTRONIC INDUSTRY.

• Our MULTICHIP PACKAGING has made us specialists in the non-standard semiconductor packages and processes.
• Our STANDARD PRODUCT LINES (SOT / SOIC / QFN.) provide our customers with consistent quality, fast cycle time, timely delivery and lower costs.
• Our CAPTIVE LINES provide the ultimate answer to our customer’s requirement for higher efficiency, faster production line responsiveness, and a guaranteed capacity.
• Strongly supported by a core team of experts with members having an average of 24 years of industry experience.
• Workforce of over 800 English proficients, multi-skilled and continuously trained employees.
• Product Range includes MCPs, MCM, and Hybrid (with SMT), COB, Opto Electronic devices, SMT assemblies, and discrete packages assembly.

ATEC's Captive Line concept provides the customer a superior, cost-effective alternative to in-house assembly operation or to outsourced services for Assembly and Final Test. It involves the set-up of a complete production line including equipment and support organization and control over process, dedicated exclusively to the customer's specific products and requirements thereby assuring the customer priority, capacity availability and set quality standards. Fifty percent (50%) of ATEC's business is from Captive Line.

A Captive Line is headed by an Operations Manager with a complement of dedicated personnel for Production, Process Engineering, Quality Control and Equipment Maintenance.

ATEC Failure Analysis and Reliability has a global perspective on the reliability requirements for the semiconductor industry. We provide all the reliability testing capabilities and product analysis capabilities required to address the complex issues arising from package, material and device interactions.

Our Objectives:

• To find the root cause of a component, material and/or process defects. May include corrective action recommendations to material suppliers.
• To analyze electronic components, especially semiconductor devices and help solve problems involving process development and engineering
• To assess the reliability risks associated new package designs using reliability methodologies
• To communicate the results to customers
• To develop immediate corrective actions on any reliability related issues identified through the analyses.

ATEC offers a wide range of services for Die Processing and Die pparation. Conducted in a Class 10K clean room environment using state-of-the-art equipment, this service include back grind, die pp, inspection, and pick and place into trays. Die inspection capabilities include commercial and military standard criteria. Special processing and shipping services are available upon request.

ATEC Die Sales Advantage:

• Provides an efficient solution to supply inspected, die for use in chip-on-board applications
• Avoids the need for the chip supplier to invest in the manufacturing infrastructure for handling and packaging bare die
• ATEC Die Sales may be packaged with test services

Details of Services:

• Class 10K Clean Room Environment
• Up to 8" Wafer Diameter
• Backgrinding to 6 mils (0.15mm) thin minimum
• Die Inspection Standards
• Die to Chip Tray or to Waffle Pack or to new Wafer Tape

ATEC offers Diverse package formats and sizes to serve the wide range portfolio of world class semiconductor manufacturers, from lead frame IC packages for through-hole and surface mounting, to the multichip solutions and stacked die circuits assembly; from legacy devices to tomorrow's system in Package solutions.

Ambient Light Photo Sensors (ALPS) - are used to measure the ambient light level in the environment as perceived by the human eye. It is designed to detect bright and dim ambient light conditions as a means of controlling the brightness of LCD display and/or keypad backlight.

ATEC is a leading Assembly service provider of Open Cavity Sensor Packages for Automotive and non-Automotive applications. ATEC has been capable in assembling this type of package since 2000 and is now producing this in mass production. Open Cavity Sensor package comes in different variety. With ATEC, these sensors are assembled to SOICs and QFNs with wide range of lead counts.

We offer other package types such as: Ceramic Packages, Hybrid, J Lead. LLCC, MCSP, MDIP, SMD Modules, Wafer Backgrind and wafer saw.

Small Outline Transistor Plastic Package. SOT-23 package or its thin version (TSOT-23) is a leaded plastic surface mount transistor component. This device has with three or more gull wings leads, bent outwards at the tip. ATEC is currently tooled for 3, 5 & 6 terminals SOT-23. ATEC SOT-23 packages are JEDEC compliant.
Short for single in-line package, a type of housing for electronic components in which the connecting pins protrude from one side. Compare with DIP and PGA. A SIP is also called a Single In-line Pin Package (SIPP).
4 Leads
9 Leads
Short for Small Outline Integrated Circuit. A SOIC package is a leaded rectangular plastic surface mount integrated circuit with eight or more gull wings leads, bent outwards at the tip. The leads are on two length sides of the package. ATEC is currently tooled for 8, 14, 16, 20, 24 & 28 terminals varying from narrow body (NB) and wide body (WB) SOIC. ATEC SOIC packages are JEDEC compliant.
32 Leads
SOIC e-Pad is a Small Outline Integrated Circuit with exposed pad on the bottom side of the package. Similar to standard SOIC package, it is a leaded rectangular plastic surface mount integrated circuit. ATEC is currently tooled for 8 terminals SOIC e-Pad. ATEC SOIC e-Pad package is JEDEC compliant.
10 Leads
20 Leads
32 Leads
CQFN
4 Leads
16 Leads
10 Leads DFN 3x3 View Technical Details
 
16 Leads DFN
16 Leads QFN
 
     
68 Leads QFN
72 Leads QFN
TO39 WITH METAL CAP

Central Test (SOT, SOIC, QFN):

Wafer Probers: TSK APM90 AL (2 units). Up to 8" wafer diameter. Probe mark & ink dot inspection, Real-time Wafer-mapping capability.

• With full spectrum instrumentation, broad configurability, and multi-site test, the Catalyst test system delivers full test coverage for a wide range of semiconductor applications, including xDSL, wireless/RF, networking, and power management with high range pins and Gigahertz speed.
• Fully integrated analog and digital instrumentation/ mixed-signal/SOC digital with data rates to 400 Mbps
• Capable for 4 to 8 inches wafer diameter

ATEC is capable of bonding copper (Cu) wire bonding since pioneering Cu wire bonding in the Philippines. Cu wire offers a significant cost advantage over a gold wire. It is also an excellent replacement for gold wire due to its similar electrical properties. Self-inductance and self-capacitance are nearly the same for gold and Cu wire and Cu wire has lower resistivity. Using Cu wire can offer improvement in applications where resistance due to the bond wire can impact circuit performance.

Copper Wire Bonding Milestones

• Started mass production of 2 million units of SOIC 8L per week in March 2007
• recognized and awarded by the customer for shipping the first 100 million units with zero customer complaints
• qualified Cu wire for SOT23 in 2009
• maintained zero customer complaint since the start of production of Cu wire bonded units
• ramped up production of copper wire bonded units to more than 14 million units per week as of November 2010
• has delivered 900M units of copper wire package by end of 2011 without any defect and claims

ATEC Failure Analysis and Reliability has a global perspective on the reliability requirements for the semiconductor industry. We provide all the reliability testing capabilities and product analysis capabilities required to address the complex issues arising from package, material and device interactions.

Our Objectives:

• To find the root cause of a component, material and/or process defects. May include corrective action recommendations to material suppliers.
• To analyze electronic components, especially semiconductor devices and help solve problems involving process development and engineering
• To assess the reliability risks associated with new package designs using reliability methodologies • To communicate the results to customers
• To develop immediate corrective actions on any reliability related issues identified through the analyses.

ATEC's has a remarkable level of package design expertise and can provide best in class leadframe and laminate designs services including the following:

• Best quality, reliable, and cost-effective designs
• Trained and experienced design engineers
• Excellent customer design collaboration to meet thermal, electrical, and mechanical requirements
• State-of-the-art design software

Collecting advanced design software tools combined with experienced Design Engineers, ATEC is known to lead in the next generation package design!

ATEC design capability has demonstrated competence in package engineering that keeps performance, low cost, and quality in mind.

• Define Design Rules and Process Controls for the customers
• Use of various design tools:
• DOE (Design of Experiment)
• SAS Jmp
• FTA (Fault Tree Analysis)
• Is/ Is Not Diagram
• Global 8D
• Problem Solving Methodology
• Use APQP Design to Production Planning
• Technical expertise per assigned process and products
• Hands-on experience in the assembly of various packages

BACKGRIND WAFER PROBER MAJOR PROCESS CONTROL MAJOR EOL ASSEMBLY

Backgrind Equipment

Normal Die with Stacked die attached on the surface

Stacked die mounted on normal die surface with the use of non-conductive epoxy

With full spectrum instrumentation, broad configurability, and multi-site test, the Catalyst test system delivers full test coverage for a wide range of semiconductor applications, including xDSL, wireless/RF, networking, and power management with high range pins and Gigahertz speed.

Fully integrated analog and digital instrumentation/ mixed-signal/SOC digital with data rates to 400 Mbps Capable for 4 to 8 inches wafer diameter

Copper wire has become the preferred materials for wire bonding interconnects in many semiconductor and microelectronic applications because of the ability to be used at smaller diameters providing the same performance as gold without the high material cost. ATEC takes pride in pioneering the development of copper wire bonding in place of gold wire in the Philippines.

Benefits of Using Copper Wire

Copper wire offers a significant cost advantage over gold wire. It is also an excellent replacement for Gold wire due to its similar electrical properties and it's almost the same in self-inductance and self-capacitance. It also has a positive impact on circuit performance because of its low resistivity.

Copper Wire Bonding Milestones of ATEC:

• Started mass production of 2 million units of SOIC 8L per week in March 2007
• recognized and awarded by the customer for shipping the first 100 million units with zero customer complaints
• qualified Cu wire for SOT23 in 2009
• maintained zero customer complaint since the start of production of Cu wire bonded units
• ramped up production of copper wire bonded units to more than 14 million units per week as of November 2010
• has delivered 900M units of copper wire package by end of 2011 without any defect and claims

• With full spectrum instrumentation, broad configurability, and multi-site test, the Catalyst test system delivers full test coverage for a wide range of semiconductor applications, including xDSL, wireless/RF, networking, and power management with high range pins and Gigahertz speed.
• Fully integrated analog and digital instrumentation/ mixed-signal/SOC digital with data rates to 400 Mbps
• Capable for 4 to 8 inches wafer diameter